Interest in semiconductor nanowires has increased over the past several years in part because of their unique optical and electrical properties and the capability of producing high quality heterostructures with large lattice mismatch on the nanometer scale. In addition, potential applications for nanowires in miniaturization of electronics and photonics has piqued interest. However, integration of semiconductor nanowire based devices has been problematic and usually requires the technologically disadvantageous (111) substrate for vertical nanowire devices or ex-situ assembly techniques to coarsely align planar nanowire devices.
One method of achieving horizontal fabrication of nanowires (in-plane with the substrate) utilizes the growth of nanowires between two parallel surfaces etched or selectively grown on a substrate resulting in a bridged nanowire structure. Spatially controlled catalyst patterning on such a surface is difficult due to the three-dimensional geometry which limits the scalability of such structures. In addition, alignment between adjacent nanowires is imperfect and difficult to control.
Nanowire growth in a direction other than the widely established <111> direction has also been previously observed. However, in general, the demonstrated yield of such nanowires is low and not easily controlled through growth conditions.